1. general description the 74hc377-q100; 74hct377-q100 is an octa l positive-edge triggered d-type flip-flop. the device features clock (cp) and data enable (e ) inputs. when e is low, the outputs qn assume the state of their corresponding dn inputs that meet the set-up and hold time requirements on the low-to-high clock (cp) transition. input e must be stable one set-up time prior to the low-to-high transition for predictable operation. inputs include clamp diodes that enable the use of current limit ing resistors to interfac e inputs to voltages in excess of v cc . this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? input levels: ? for 74hc377-q100: cmos level ? for 74hct377-q100: ttl level ? common clock and master reset ? eight positive edge-triggered d-type flip-flops ? complies with jedec standard no. 7a ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options ? specified from ? 40 ? cto+85 ? c and from ? 40 ? cto+125 ? c 74hc377-q100; 74hct377-q100 octal d-type flip-flop with data enable; positive-edge trigger rev. 1 ? 21 october 2013 product data sheet
74hc_hct377 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 21 october 2013 2 of 18 nxp semiconductors 74hc377-q100; 74hct377-q100 octal d-type flip-flop with data enable; positive-edge trigger 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74hc377d-q100 ? 40 ? c to +125 ? c so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 74hct377d-q100 74HC377DB-Q100 ? 40 ? c to +125 ? c ssop20 plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1 74hct377db-q100 74hc377pw-q100 ? 40 ? c to +125 ? c tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 74hct377pw-q100 fig 1. functional diagram mna606 outputs ff1 to ff8 q0 q1 q2 q3 q4 q5 q6 q7 19 16 15 12 9 6 5 2 d 0 d1 d2 d3 d4 d5 d6 d7 cp e 18 11 1 17 14 13 8 7 4 3
74hc_hct377 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 21 october 2013 3 of 18 nxp semiconductors 74hc377-q100; 74hct377-q100 octal d-type flip-flop with data enable; positive-edge trigger fig 2. logic symbol fig 3. iec logic symbol mna918 d0 d1 d2 d3 d4 d5 d6 d7 e cp q0 q1 q2 q3 q4 q5 q6 q7 11 1 19 16 15 12 9 6 5 2 18 17 14 13 8 7 4 3 mna919 19 16 15 12 9 6 5 11 1c2 1 g1 2d 2 18 17 14 13 8 7 4 3 fig 4. logic diagram mna610 d0 q0 d ff1 q cp cp e d1 q1 d ff2 q cp d2 q2 d ff3 q cp d3 q3 d ff4 q cp d4 q4 d ff5 q cp d5 q5 d ff6 q cp d6 q6 d ff7 q cp d7 q7 d ff8 q cp
74hc_hct377 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 21 october 2013 4 of 18 nxp semiconductors 74hc377-q100; 74hct377-q100 octal d-type flip-flop with data enable; positive-edge trigger 5. pinning information 5.1 pinning 5.2 pin description 6. functional description [1] h = high voltage level; h = high voltage level one set-up time prior to the low-to-high clock transition; l = low voltage level; l = low voltage level one set-up time prio r to the low-to-high clock transition; x = don?t care; ? = low-to-high clock transition. fig 5. pin configuration + & |